AMD’s upcoming 3D V-Cache shown to improve bandwidth with minimal latency increase

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Highly anticipated: Speculation around AMD’s new 3D V-Cache technology has swirled ever since Dr. Lisa Su gave us a sneak peek at Computex 2021. Since then, AMD and tech enthusiasts have remained cautiously optimistic regarding claims that the new chiplet-stacking approach can yield substantial performance gains with minimal impact to latency, responsiveness, and overall functionality. A recent test of an EPYC processor with V-Cache is giving early indication that AMD’s performance uplift claims may just hold true.

No one was quite sure what to expect when AMD announced their 3D V-Cache technology at Computex last summer. While some enthusiasts saw the substantial increase in cache as an exciting development, others in the community found themselves upset that the new offerings would not offer substantial increases in clock speed, improvements in power draw, etc. Last Friday tech news outlet Chips and Cheese published results of their initial testing with one of AMD’s new Milan-X processors with 3D V-Cache, the server-oriented EPYC 7V73X. And so far, things look promising.

According to the site’s summary, AMD has managed to substantially increase a processor’s cache size (768MB) in comparison to the previous Milan family of processors (256MB). Testing by Chips and Cheese reports impressive performance from the stacked CPU and much larger L3 cache without incurring any significant increase to cache and memory latency. Initial testing shows the latency penalty keeping the increase somewhere between three to four cycles.

If these preliminary findings hold true for AMD’s upcoming AM4 and AM5 releases, such as the Ryzen 7 5800X3D, then the chipmaker will undoubtedly continue exploring the possibilities and benefits associated with 3D chip stacking.

AMD’s current 3D stacking technology involves bonding a single V-Cache chiplet to a processor’s existing core complex die (CCD) and cache. As the technology matures It may be possible for future architectures to further expand their L3 cache capabilities using additional chiplets.

We’ll have to wait and see what the future holds, but if the EPYC-based results are any indication of what is possible, then AMD could deliver another sizeable performance increase with their next round of CPUs.

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